This invention relates to non-volatile memory elements, and more particularly to highly reliable non-volatile memory elements capable of reducing the rate of occurrence of defective data retention.
FIG. 4 is a plan view, showing the basic structure, of a prior art non-volatile memory element 300, as an example of semiconductor memory element capable of electrically writing and erasing data, which comprises an EEPROM of the so-called FLOTOX (floating gate tunnel oxide) type. FIG. 5 is a sectional view taken along line 5--5 of FIG. 4, showing the memory element 300 as comprising a floating gate electrode layer 51, a control gate electrode layer 53, an insulating inter-layer film 54, an insulating film 55, a tunnel oxide film 52, source/drain regions 56, 57 and 58 and an impurity diffusion region 59. The source-drain regions 56, 57 and 58 and the impurity diffusion region 59 are formed at specified intervals on the main surface of a p-type silicon substrate 40. The floating gate electrode layer 51 is formed over the area from the the source/drain region 56 to the impurity diffusion region 59 with the insulating film 55 in between. The control gate electrode layer 53 is formed above the floating gate electrode layer 51 with the insulating inter-layer film 54 in between. The floating gate electrode layer 51 has a protruding part which is formed above the impurity diffusion region 59 with the tunnel oxide film 52 in between.
In addition, the memory element 300 also comprises a selection gate 50 and a bit line 61. The selection gate 50 is formed over the region from the source/drain region 57 to the source/drain region 58. The region sandwiched between the source/drain regions 57 and 58 becomes conductive and non-conductive in accordance with the signal inputted to the selection gate 50. The source/drain region 58 has a contact opening 62 formed for taking out the voltage and is connected to the bit line 61 therethrough. The data item stored in the transistor of which the floating gate electrode layer 51 and the control gate electrode layer 53 are constituents is outputted to an external peripheral device through the bit line 61.
The non-volatile memory element 300 thus structured has the following three operating modes: "write", "erase" and "read". A data item is stored according to the condition of charge on the floating gate electrode layer 51. Charging and discharging of the floating gate electrode layer 51 are carried out by the F-N (Fowler-Nordheim) tunnel current through the tunnel oxide film 52.
In the erase mode, a (high) erase voltage VPP is applied to the control gate electrode layer 53 and the selection gate 50 and the bit line 61 is grounded at the same time such that the source/drain region 58 is kept at the ground potential. As a result, electrons are injected from the impurity diffusion region 59 to the floating gate electrode layer 51, and the floating gate electrode layer 51 becomes negatively charged. This causes the threshold voltage Vth of the memory transistor formed below the control gate electrode layer 53 to become higher. This condition will be hereinafter referred to as the erased condition ("1"). In the write mode, the control gate electrode layer 53 is kept at the ground potential and a high voltage is applied to the selection gate 50 and the source/drain region 58. As a result, the electrons accumulated in the floating gate electrode layer 51 are ejected to the impurity diffusion region 59 and the floating gate electrode layer 51 becomes positively charged. This causes the threshold voltage Vth to become lower, and this condition will be referred to as the written condition ("0").
In the read mode, an intermediate voltage between the threshold voltages Vth in the erased and written conditions is applied to the control gate electrode layer 53. If the floating gate electrode layer 51 is in the positively charged condition ("0"), a channel is formed in the region ER3 between the impurity diffusion region 59 and the source/drain region 56. If the floating gate electrode layer 51 is in the negatively charged condition ("1"), no channel will be formed in the region ER3. Thus, the conditions "0"(wherein the region ER3 is conductive) and "1" (wherein the region ER3 is non-conductive) can be read out, depending on the current which flows through the bit line 61 when a voltage is applied to the control gate electrode layer 53.
In summary, the prior art memory element 300 stores information by using a tunnel current to change the charged condition of the floating gate electrode layer 51. In order to inject and discharge electrons into and from the floating gate electrode layer 51; however, it is necessary to apply a high voltage. If write and erase processes are repeated many times, therefore, the tunnel oxide film 52 suffers from a voltage stress, and this causes its degradation and destruction and gives rise to the problem of defective data retention because the electrons injected into the floating gate electrode layer 51 leak out through the tunnel oxide film 52.
FIG. 6 shows the relationship between faulty operations and the frequency of use for such a prior art non-volatile memory element, the vertical axis representing the rate of occurrence of faulty operations and the horizontal axis representing the frequency of use. This curve is sometimes referred to as a bathtub curve, of which the part corresponding to the initial period indicated by symbol T.sub.0 may be referred to as the initial fault period. The faults which appear relatively early during this period immediately after the use is started are primarily caused by the production processes. The second period indicated by symbol T.sub.1 may be referred to as the accidental fault period. The faults which take place during this period are those which come about sporadically and relatively soon after the initial fault period. The rate of occurrence of faults is determined by the design and represents the reliability which is peculiar to the product. The final period indicated by symbol T.sub.2 may be referred to as the wear fault period in which the number of faults increases with time, caused by wear and tear as well as material fatigue phenomena inclusive of the destruction of the tunnel oxide film 52. FIG. 6 shows that there is a rapid increase in the number of faults due to the destruction of the tunnel oxide film of a prior art non-volatile memory element according to the frequency of its use. In other words, prior art memory elements of this type fail to store data reliably after they are used very frequently. This affects the reliability of the memory device using such elements.